Potential Use of RTL Co-Simulation

Potential Use of RTL Co-Simulation Department of ECE, SRMIST, Vadapalani, Chennai India. S. Karthik* K. Priyadarsini Department of CSE, VISTAS, Pallavaram, Chennai India.

This paper’s objective is to highlight the potential use of C/RTL Co-Simulation and application of it in satisfying the time constraints involved in verification of industrial, complex, monolithic. Co-Simulation performed in Xilinx software has provided a platform for further analysis of designs. Steps before performing co-simulation has provided statistical data about how much resources the system design requires which can be further analyzed, part-by-part, using profiling method. The profiling allows demarcation of a distinctive line between resource-intensive processes and time-intensive processes. A further study into this matter would purge the need of resource-intensive and time-consuming devices. This could be a small step towards attaining a level of production where the outcome is a better device and error-less production of these devices.
10 30 2019 586 588 CC-BY-NC-ND 4.0 10.35940/BEIESP.CrossMarkPolicy www.ijitee.org true 10.35940/ijitee.L3463.1081219 https://www.ijitee.org/portfolio-item/L34631081219/ https://www.ijitee.org/wp-content/uploads/papers/v8i12/L34631081219.pdf