High-Performance ADC Design Using Fast Prediction Logic with Dynamic Clock Stretching Mechanism

In high-performance ADC designs, time-borrowing techniques are commonly utilized to reduce timing errors. A new dynamic flip-flop conversion mechanism has been developed in this work. The important contribution of this work is to dynamically convert flip-flops to transparent latches for time savings while avoiding setup time violations. In a continuous structure with a critical path and a critical feedback path, dynamic clock stretching structures cannot prevent timing violations. The DTEA technique is proposed in this work to overcome the above concerns. The proposed DTEA technique is compared to existing techniques in terms of performance enhancement and overhead area, and it is observed that there is an overall performance improvement. Based on the obtained results, it is observed that the proposed methodology improves pre-layout and post-layout simulation performance by an average of 20.2 percent and 14.8 percent, respectively.