An Optimized Retiming-based FIR Filter Architecture using Efficient Multipliers and Adders

An efficient higher-order filter architecture is designed and implemented
for ECG signal processing applications. To prune the latency of the architecture, the retiming technique
is considered for the design of less memory type Finite Impulse Response (FIR) filter architecture.
The optimized multipliers and adders are key blocks in the filter architecture to increase
the latency and Power Consumption (PC).