Embedded Cost-Effective VLSI Structures with Low-Power Scheduling and Spiking Convolutional Neural Network Inference
Rao, A Purnachandra and Ali Samhan, Ahmad Abdelhafiz and D, Pradeep Kumar and Kiran, M Sreerama and Dharmarajan, K and Yakaiah, P (2025) Embedded Cost-Effective VLSI Structures with Low-Power Scheduling and Spiking Convolutional Neural Network Inference. In: 2025 2nd International Conference on Artificial Intelligence and Knowledge Discovery in Concurrent Engineering (ICECONF), Chennai, India.
Pradeep Kumar - Embedded_Cost-Effective_VLSI_Structures_with_Low-Power_Scheduling_and_Spiking_Convolutional_Neural_Network_Inference.pdf
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Abstract
The Cost-Effective VLSI Structures with LowPower Scheduling and Spiking Convolutional Neural
Network Inference (CVLPSC) process features a highperformance architecture that integrates advanced
fingerprint sensing with robust cryptographic security and
energy-efficient engineering for real-time applications. It
includes a highly sensitive sensor structure designed to
detect minute capacitive changes from fingerprints,
optimized with shielding and buffering to improve
performance while reducing noise. The pipelined charge
integration technique facilitates rapid image capture,
alongside security measures such as Kerckhoff’s principle
and SUCs, which enhance encryption key generation to
defend against attacks. The SCNN modules provide
strong processing capabilities, able to perform 100-
million-pixel computations per second. The following
metrics: energy consumption analysis, system energy
comparison, throughput calculation, delay calculation,
and routing overhead, several existing models such as
EFMIL, CHVST, and ESDSB
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Subjects: | Computer Applications > Information Technology |
| Domains: | Computer Science |
| Depositing User: | Mr IR Admin |
| Last Modified: | 07 May 2026 12:05 |
| URI: | https://ir.vistas.ac.in/id/eprint/13928 |
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